1. Field of the Invention
The present invention relates to semiconductor devices and a method of manufacturing thereof, and more particularly to the structure of a vertical type MOS (Metal Oxide Semiconductor) device having a gate electrode formed in the step portion of an active layer pattern formed by epitaxial growth on a semiconductor substrate and a method of manufacturing thereof.
2. Description of the Background Art
In accordance with the increase in integration density of MOS type semiconductor integrated circuit devices, the channel length of a MOS type field effect transistor implementing the device is significantly reduced. Also, the channel width (transistor width) has become smaller.
A method of manufacturing a conventional MOS type field effect transistor will be explained hereinafter with reference to FIGS. 19A-19C.
An element isolation region 2 is formed by the so-called LOCOS (Local Oxidation of Silicon) method on the main surface of a p type semiconductor substrate 1. Then, an oxide film 3a is formed by thermal oxidation on an active region surrounded by element isolation region 2. A polycrystalline, silicon film 4a having impurities doped and then an oxide film 5a are deposited by CVD (Chemical Vapor Deposition) method all over semiconductor substrate 1, followed by the patterning of a resist film 6 (FIG. 19A).
Etching is applied anisotropically with resist film 6 as a mask to pattern a gate insulation film 3, a gate electrode 4, and an insulation layer 5. Using gate electrode 4 and insulation layer 5 as a mask, n type impurities are implanted to form an impurity layer 7 of low concentration (FIG. 19B).
An oxide film is deposited all over semiconductor substrate 1 by the CVD method, whereby etching is applied anisotropically to form a side wall spacer 8 at the sides of gate electrode 4 and insulation layer 5. Then, n type impurities are implanted with insulation layer 5 and side wall spacer 8 as a mask to form an impurity layer 9 of high concentration (FIG. 19C).
If the channel length of such a MOS type field effect transistor formed in the above-described manner is reduced drastically, the generation of hot electrons becomes significant due to the intensive electric field between the source and drain. These hot electrons are introduced and accumulated in the gate insulation film so that the characteristic is degraded. Thus, there is a problem in a MOS type integrated circuit device implemented with a MOS type field effect transistor of the conventional planar structure that increase in integration density is limited due to the tradeoff between the minimum channel length and degradation in transistor characteristic.
There was also another problem that the current capacity (conductance) of the transistor is decreased due to reduction in the channel width.
A vertical type MOS field effect transistor is proposed where a projection pattern of monocrystalline silicon is formed on the main surface of the silicon substrate with the side of the projection serving as a channel region for achieving sufficient channel length without characteristic degradation even when the area of the transistor is drastically reduced in accordance with the increased scale of integration of a MOS type integrated circuit device.
A conventional method of manufacturing such a vertical type MOS field effect transistor will be described hereinafter with reference to FIGS. 20A-20F.
An insulation film 12 of silicon dioxide, for example, is formed to a thickness of approximately 0.5-2 .mu.m on a p type silicon substrate 11. A rectangular opening 13 with a dimension of approximately 3 .mu.m for one side is formed corresponding to the drain region of each transistor in insulation film 12 by photolithography. Using a mixed gas of, for example, dichlorosilane of the source gas of the silicon, hydrochloric acid of reaction gas, and hydrogen of carrier gas, a monocrystalline silicon layer 104 is grown to a thickness of approximately 0.5-2 .mu.m which is substantially equal to that of insulation film 12 within opening 13 of insulation film 12 on the face of the exposed silicon substrate 11 by the conventional selective epitaxial growth technique of silicon where dichlorosilane is thermal decomposed at a temperature of approximately 1100.degree.-1200.degree. C. (FIG. 20A).
Insulation film 12 is then dissolved by wet etching to form a monocrystalline silicon projection pattern 14 of 0.5-2 .mu.m in height on the surface of silicon substrate 1 (FIG. 20B).
A gate insulation film 15 is formed over the surface of monocrystalline silicon projection pattern 14 and over the exposed face of silicon substrate 11. Then, a polycrystalline silicon layer 106 is formed on silicon substrate 11 by vapor growth, to which impurities of n type, for example, are implanted thereto (FIG. 20C).
Next, polycrystalline silicon layer 106 is etched until the surface of gate insulation film 15 is exposed by conventional reactive ion etching process to form a gate electrode 16. The etching is further continued till the exposed gate insulation film 15 is removed (FIG. 20D).
A through oxide film 17 is formed on the silicon exposed surface, whereby n type impurities of high concentration are ion-implanted therethrough with gate electrode 16 as a mask. The implanted ions are subjected to activation process to form an n.sup.+ type drain region 18 on the surface of monocrystalline silicon projection pattern 14 and an n.sup.+ type source region 19 at the surface of silicon substrate 11 (FIG. 20E).
Through oxide film 17 is then removed in a conventional manner and an oxide film 20 for impurity blocking is formed on the silicon exposed surface. An interlayer insulation film 21 is then formed on the semiconductor substrate with a contact hole 22 therein for drain region 18. Next a drain interconnection 23 is formed extending over contact hole 22 and interlayer insulation film 21 (FIG. 20F). A plane layout diagram of the structure of FIG. 7F is shown in FIG. 21.
The above-described manufacturing method is described, in Japanese Patent Laying-Open No. 63-153864, for example, where the surface layer including the side face of the monocrystalline silicon projection pattern is applied with thermal oxidation, followed by eliminating the formed thermal oxide film for eliminating the growth defect generated in the side face of the monocrystalline silicon projection pattern.
Because a vertical type MOS field effect transistor formed by the above-described manufacturing steps has a silicon epitaxial film of rectangular shape on the silicon substrate, there was a problem that the threshold voltage is increased (narrow channel effect) due to the width of the gate electrode formed in the step portion becoming smaller according to a more minute pattern in larger scale integration.
The narrow channel effect is a phenomenon where the absolute value of the threshold voltage becomes higher by reduction in the channel width in a direction perpendicular to the direction of the channel length. The cause will be described hereinafter with reference to FIGS. 22A and 22B.
When the ratio of the width of channel region 103 (w in the figure) sandwiched by element isolation regions 102 formed on the surface of silicon substrate 101 to the depth of channel region 103 receiving effect of an electric field from gate electrode 103 (d in the figure), i.e. w/d, is relatively great as shown in FIG. 22A, the magnitude of region s.sub.2 located below element isolation region 102 is negligibly small with respect to the region s.sub.1 right beneath the active region surrounded by element isolation region 102 out of the region affected by the gate voltage applied to gate electrode 104. This means that the threshold voltage is independent of the influence of region s.sub.2 and depends upon the magnitude of region s.sub.1. When w/d is relatively small as shown in FIG. 22B, the magnitude of region s.sub.2 is relatively great with respect to the magnitude of region s.sub.1 and cannot be neglected. Therefore, the gate voltage required to invert the conductivity type of region s.sub.1 is greater in the case of FIG. 22B than in the case of FIG. 22A, resulting in a higher threshold voltage.
There was also a problem that the pattern of the rectangular shape easily approximates a circular shape so that a rectangular pattern conforming to the former design is hard to obtain due to diffraction effect of light used in the lithography step of forming the pattern of a silicon epitaxial film in accordance with miniaturization.